The present disclosure relates generally to the field of semiconductor devices, and more particularly to methods for forming chamferless vias.
As the dimensions of integrated circuits shrink, minimum insulator requirements become important and via to line spacing must be controlled. Chamferless vias can be fabricated as a solution; however, conventional approaches to forming chamferless vias have certain weaknesses such as: (i) resulting in increased critical dimensions during wet clean; (ii) leaving residual plug fill materials; (iii) resulting in differing chamfer angles between dense and isolated vias; (iv) resulting in liner punch through at the trench bottom; and/or (v) damaging and removing dielectric layers.